Digital phase detectors are used in phase-locked loops and delay-locked loops. Phaselocked loops circuits are widely used in electronic systems to generate an accurate replica of an incoming signal, or for frequency synthesis. For example, in a computer, a phase-locked loop is to used by a microprocessor to generate an on-chip clock signal from an off-chip clock signal. Within the phase-locked loop, the digital phase detector is used to generate an error voltage proportional to the phase difference between a reference signal and a signal generated by a voltage controlled oscillator (VCO). The error voltage is use to tune the VCO so that the VCO is phase locked with the reference signal.
Delay-locked loops are also widely used in electronic systems. Delay-locked loops can be used realign the edges of internal clock and data signals which have been skewed during the distribution of the signals. Circuitry through which the internal clock and data signals are distributed induce undesirable delay which causes clock and data signals to reach destination circuit elements delayed in time. The delay-lock loop provides additional delay in the distributed signals so that the edges of the signals are aligned with, for example, a master clock signal. Within a delay-locked loop, the phase detector is used to generated an error signal which is proportional to the phase difference between the master clock and the distributed signal. Typically, the error signal is used to tune a programmable delay line which re-aligns the edges of the distributed signal with the master clock.
FIG. I shows a digital phase detector 10 which includes a reference clock input Ref.sub.-- CLK, a feedback signal input FDB.sub.-- CLK and an output Detector.sub.-- Out. The digital phase detector 10 generates a signal at the output Detector.sub.-- Out which reflects the phase differences between the reference clock input Ref.sub.-- CLK and the feedback signal input FDB.sub.-- CLK. Generally, the signal Detector.sub.-- Out at the output of the digital phase detector 10 will only change states or voltage levels upon the occurrence of an edge or a voltage potential level of either the signal input Ref.sub.-- CLK or the signal input FDB.sub.-- CLK.
FIG. 2 includes Traces 2A, 2B, 2C which represent signals at the inputs and the resultant output of the digital phase detector 10 shown in FIG. 1. Trace 2A shows a reference clock input Ref.sub.-- CLK signal. Trace 2B shows a feedback signal input FDB.sub.-- CLK signal. Trace 2C shows an output Detector.sub.-- Out response to the inputs shown in Traces 2A, 2B.
Some key features of the signals should be noted. First, if the output Detector.sub.-- Out is at a lower of two states upon the occurrence of a positive edge at the reference clock input Ref.sub.-- CLK signal, the output Detector.sub.-- Out will transition to a higher state. If the output Detector.sub.-- Out is at the higher of the two states upon the occurrence of a positive edge at the reference clock input Ref.sub.-- CLK signal, the output Detector.sub.-- Out will remain at the higher state. If the output Detector.sub.-- Out is at the higher state upon the occurrence of a positive edge at the feedback signal input FDB.sub.-- CLK signal, the output Detector.sub.-- Out will transition to the lower state. If the output Detector.sub.-- Out is at the lower state upon the occurrence of a positive edge at the feedback signal input FDB.sub.-- CLK signal, the output Detector.sub.-- Out will remain at the lower state. Further, if the reference clock input Ref.sub.-- CLK signal and the feedback signal input FDB.sub.-- CLK signal both transition from the lower state to the higher state at approximately the same time, the output Detector.sub.-- Out toggles to the one of the two states the output Detector.sub.-- Out is not in upon the transition of the two inputs.
Dashed lines 20, 24 show the output Detector.sub.-- Out transitioning to a high state due to a positive edge transition of the reference clock input Ref.sub.-- CLK signal. Dashed lines 22, 26, 32 show the output Detector.sub.-- Out transitioning to a low state due to a positive edge transition of the feedback signal input FDB.sub.-- CLK signal. Dashed lines 28, 30 depict a dead zone of the digital phase detector. The output Detector.sub.-- Out of the phase detector will toggle due to the occurrence of positive transitioning edges of both the reference clock input Ref.sub.-- CLK signal and the feedback signal input FDB.sub.-- CLK signal within the dead zone of the digital phase detector. The dead zone of the phase detector is the period of time defined by the dashed lines 28, 30 in which the output Detector.sub.-- Out of the phase detector will toggle if the two inputs transition high. If the positive edges of the two inputs are separated apart in time so that either positive edge is not in the dead zone time defined by the dashed lines 28, 30, the output Detector.sub.-- Out will not toggle. Rather, the phase detector will respond to positive edge transitions of the inputs as previously described.
The larger the size of the dead zone period of time defined by the dashed line 28, 30, the lower the operational frequency of the digital phase detector. Therefore, it is desirable to minimize the size of the digital phase detector dead zone.
The reference clock input Ref.sub.-- CLK signal to the digital phase detector can be noisy. Prior art digital phase detectors either require a limitation on the amount of noise within the reference clock input signal, or additional circuitry is required to filter the reference clock input signal.
The prior art digital phase detectors as shown in FIG. 1 can experience instabilities. The instabilities can increase the time required to obtain lock in either phase-locked loops or delay-locked loops.
It is desirable to have a digital phase detector which offers high sensitivity and provides a phase detector dead zone that is smaller than previously possible. The digital phase detector would provide filtering of the reference clock signal input to the digital phase detector. Further, the digital phase detector would provide a reset condition to avoid instabilities of the digital phase detector.